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Virage Logic Introduces Ultra-Low-Power Semiconductor IP Platform

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Fremont CA (SPX) Jun 29, 2004
One of the unrelenting challenges facing system-on-chip (SoC) designers today is power management, particularly in low-power, battery-operated microelectronics that serve as the basis for any number of ubiquitous consumer electronics products such as cell phones, personal digital assistants (PDAs) and handheld gaming platforms.

Ironically, the one element in SoCs that has not shrunk along with process geometries is static power. In fact, it has grown exponentially, in inverse proportion to the overall size of the SoC.

To help designers address this challenge, Virage Logic Corp., a leading provider of best-in-class semiconductor IP platforms, announced on Monday, IPrima Mobile, an application-optimized semiconductor IP platform that significantly minimizes and effectively manages power dissipation without paying a performance penalty.

IPrima Mobile is the first offering in Virage Logic's IPrima family of application-optimized semiconductor IP platforms.

"Portable consumer and wireless personal communication products will be market drivers for the semiconductor industry over the next five years. Growth rates for many of these products will average more than 30 percent annually," said Morry Marshall, vice president strategic technologies at Semico Research Corporation.

"The potential power savings and longer battery life offered by the IPrima Mobile platform will provide a real competitive advantage to Virage Logic's customers."

The IPrima family of application-optimized semiconductor IP platforms brings together a wide range of technology-leading IP components in a single, integrated IP platform comprising memories, logic and I/Os.

IPrima Mobile enables a broad range of power management methods to control both static and dynamic power consumption; including such advanced optimization techniques as full block-level voltage islands, clock gating, mixed-transistor threshold voltage support, voltage frequency scaling, back biasing and state retention standby mode.

With IPrima Mobile, designers can determine the optimum level of power dissipation reduction for their application's performance requirements.

"IPrima Mobile builds on Virage Logic's three-plus years of silicon-proven low-power IP products to provide SoC designers with a single, integrated IP platform that enables them to efficiently develop consumer products with longer battery life and lower electromagnetic interference (EMI) emissions," said Jim Ensell, vice president of marketing at Virage Logic.

"By delivering up to 20X reduction in static and 80 percent reduction in dynamic power dissipation, IPrima Mobile gives our customers the ability to rocket past their competitors in terms of battery life, one of the key features consumers care about."

"We have used Virage Logic memories with many of our designs; however, our latest SignaKlara(TM) embedded technology used in a wide range of portable and wearable devices required ultra-low-power and ultra-miniature IP," said Peter Balsiger, president of Dspfactory SA.

"We selected the IPrima Mobile memories and standard cells after an extensive evaluation resulted in significant power and area savings that are required for our latest designs."

To fully maximize IPrima Mobile's advanced power-optimization features, Virage Logic has established strategic partnerships with leading electronic design automation (EDA) tools developers, IP companies and foundries.

This ensures a complete and reliable design flow, support for protocols such as the ARM(R) Intelligent Energy Management(TM) (IEM) technology, and optimization of performance and energy dissipation with respect to manufacturing costs.

"Optimizing power consumption has become a system-level issue. To generate the best combination of optimal energy dissipation and adequate computing performance, enhanced EDA tools and optimized IP platforms must work smoothly together," said Eric Filseth, vice president of marketing for digital IC implementation at Cadence Design Systems.

"Virage Logic's IPrima Mobile was designed to work with our Cadence Encounter low-power design flow, the leading solution to analyze and optimize power for nanometer designs."

"It's significant that Virage Logic is making its first IPrima Mobile platform offering available on TSMC's 0.13-micron process," said Edward Wan, senior director of product marketing in design services at TSMC.

"The consumer electronics market is an important one and IPrima Mobile's power-optimization techniques, together with TSMC's outstanding manufacturing capabilities, will provide significant benefits."

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